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ÁýÀûȸ·Î
¿¬±¸½ÇÀÇ BK21°ü·Ã»çÇ×

BK21°ü·Ã»ç¾÷
¿¬±¸¼º°ú(*´Â BK21 Âü¿©¿¬±¸¿ø)


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[1] You-Jin Cha*, Seung-Hoon Lee*,
and Jin-Kug Lee, "Digitally-controlled automatic gain control circuits for CMOS CCD camera
interface," IEE Electronics Letters, vol. 35, no, 22, pp.
1909-1910, Oct. 1999. [SCI]
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[2] Young-Deuk Jeon* and Seung-Hoon
Lee*, "Acquisition time minimization techniques for high-speed
analog signal processing," IEE Electronics Letters, vol. 35,
no. 23, pp. 1990-1991, Nov. 1999. [SCI]
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[3] Jin Park, Seung-Chul Lee*, and
Seung-Hoon Lee*, "3 V 10b 70 MHz CMOS D/A converter for video
applications," IEE Electronics Letters, vol. 35, no. 24, pp.
2071-2073, Nov. 1999. [SCI]
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[4] Tae-Hwan Oh* and Seung-Hoon
Lee*, "Single-chip CMOS CCD
camera interface based on digitally-controlled capacitor-segment
combination," IEEE Trans. on Circuits Syst. II, vol. 47, no.
11, pp. 1338-1343, Nov. 2000. [SCI]
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[5] Jin Park, Seung-Chul Lee*,
Jin-Sik Yoon*, and Seung-Hoon Lee*, "A 3V 10b 100MS/s
digital-to-analog converter for cable modem applications," IEEE
Trans. on Consumer Electronics, vol. 46, no, 4, pp. 1043-1047, Nov.
2000. [SCI]
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[6] Seung-Ho Lee*, Jung-Woong Moon*,
and Seung-Hoon Lee*, "An 8b 52MHz double-channel CMOS subranging A/D
converter for DSL applications," IEICE Trans. on Electronics,
vol. E84-C, no. 4, pp. 470-474, April 2001. [SCI]
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[7]
S. H. Lee* and J. S. Lee*,
"Comments on comments on
interstage gain-proration technique
for digital-domain multistep
ADC calibration," IEEE
Trans. Circuits Syst. II,
Vol 48, No. 7, pp. 745-749,
July 2001. [SCI]
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[8]
J. S. Lee*, S. H. Joo*,
and S. H. Lee*, "Resolution
enhancement techniques for high-speed
multi-stage pipelined ADC's
based on a multi-bit multiplying
DAC," IEICE Trans. on
Electronics, vol. E84-C,
No. 8, pp. 1092-1099, Aug. 2001.
[SCI]
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[9]
S. C. Lee* and S. H. Lee*,
"A Low-Ripple Switched-Capacitor
DC-DC up Converter for Low-Voltage
Applications," IEICE
Trans. on Electronics, vol.
E84-C, No. 8, pp. 1100-1103,
Aug. 2001. [SCI]
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[10]
J. W. Moon* and S.H. Lee*,
"An 8b 200MHz Time-Interleaved
Subranging ADC Based on a Single-Poly
Digital CMOS Process,"
IEICE Trans. on Electronics,
Jan. 2003 to be published. [SCI]
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[1] "CMOS operational amplifiers having reduced
power consumption requirements and improved phase margin
characteristics," Dong-Young Chang, You-Mi Lee, Seung-Hoon Lee*,
Geun-Soon Kang, Hee-Cheol Choi, Date of Patent : 2000. 4. 18., Patent
Number : 6052025, Filing Country : U.S.
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[2] "Analog/Digital converting circuit," Dong-Young
Chang, Jae-Yup Lee, Seung-Hoon Lee*, Yong-In Park, Seung-Woo Park, Date
of Patent : 2000. 10. 3., Patent Number : 6127958, Filing Country : U.S.
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[1] You-Jin Cha*, Jin-Kug Lee, Jin
Park, and Seung-Hoon Lee*, "Digitally-controlled
automatic gain control circuits for CMOS CCD electronic cameras," The
6th Intl. Conf. on VLSI and CAD, Korea, pp. 342-345, Oct. 1999.
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[2] Seung-Chul Lee*, Joon-Seok Lee*,
Sung-Ho Lee*, and Seung-Hoon Lee*, "A 3 V 200 MHz PLL with a low-noise VCO based on a
power-efficient low-ripple DC-DC converter," The 6th Intl. Conf.
on VLSI and CAD, Korea, pp. 346-348, Oct. 1999.
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[3] Young-Deuk Jeon*, Byeong-Lyeol
Jeon, Seung-Chul Lee*, Sang-Min Yoo*, and Seung-Hoon Lee*, "A 12b 50 MHz 3.3 V CMOS Acquisition Time Minimized A/D
Converter," ASP-DAC 2000 (Asia and South Pacific Design
Automation Conference 2000), Japan, pp. 613-616, Jan. 2000.
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[4] Y.D. Jeon*, S.C. Lee*, S.M.
Yoo*, and S.H. Lee*, "Acquisition-time
minimization and merged-capacitor switching techniques for sampling-rate
and resolution improvement of CMOS ADCs," ISCAS (Intl. Sym. on
Circuits and Syst.) 2000, Geneva, pp. III 451-454, Switzerland, May
2000.
|

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[5] Seung-Chul Lee*, Jin Park,
Jin-Sik Yoon*, Jung-Hee Song, and Seung-Hoon Lee*, "A 3V 10b 100MS/
digital-to-analog converter for cable modem applications," AP-ASIC
2000 (Asia Pacific Conf. on ASICs), Korea, pp. 203-205, Aug. 2000.
|

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[6] Seung-Chul Lee*, Dong-Soo Park*,
Jung-Hee Song, Myung-Whan Choi, and Seung-Hoon Lee*, "A low-ripple switched capacitor DC-DC up converter for
low-voltage applications," AP-ASIC 2000 (Asia Pacific Conf. on
ASICs), Korea, pp. 13-16, Aug. 2000.
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[7]
S.M.
Yoo*, T.H. Oh*, J.W. Moon*,
S.H. Lee*, and U. Moon, "A
2.5V 10b 120MSample/s CMOS pipelined
ADC with high SFDR," Custom
Integrated Circuits Conference
(CICC) 2002, Orlando, Florida,
pp. 441-444, May 2002.
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[8]
Seung-Hoon
Lee* (Keynote Speech), "8b-12b
50-200MS/s low-power pipelined
ADC design techniques for SoC
applications," International
Conference on Circuits / Systems,
Computers and Communications
2002 (ITC-CSCC 2002), Phuket,
Thailand, August 2002.
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[9]
Seung-Hoon
Lee*, "An 11b 70MHz 1.2mm
49mW 0.18um CMOS ADC with on-chip
current/voltage references,"
28th European Solid-State Circuits
Conference (ESSCIRC) 2002, Florence,
Italy, September 2002.
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[10]
Sang-Min Yoo*, Jong-Bum Park*,
Hee-Suk Yang*, Hyuen-Hee Bae,
K. H. Moon, H. J. Park, Seung-Hoon
Lee*, and J. H. Kim, "A
10b 150MSample/s 123mW 0.18um CMOS
Pipelined ADC," IEEE ISSCC
Digest of Technical Papers,
Feb. 2003, to be presented.
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[1] À¯»ó¹Î*, Àü¿µµæ*, À̽ÂÈÆ*, "CMOS A/D º¯È¯±âÀÇ »ùÇøµ
¼Óµµ ¹× ÇØ»óµµ Çâ»óÀ» À§ÇÑ º´ÇÕ Ä³ÆÐ½ÃÅÍ ½ºÀ§Äª±â¹ý" ´ëÇÑÀüÀÚ°øÇÐȸ ³í¹®Áö, Á¦37±Ç, SCÆí, Á¦6È£, pp.
405-411, 2000³â 11¿ù.
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[2] ¹ÚÁ¾¹ü*,
À¯»ó¹Î*, ¾çÈñ¼®*, Áö¿ë, À̽ÂÈÆ*,
"³ôÀº SFDRÀ» °®´Â 2.5V
10b 120MS/s CMOS ÆÄÀÌÇÁ¶óÀÎ
A/D º¯È¯±â" ´ëÇÑÀüÀÚ°øÇÐȸ
³í¹®Áö, Á¦39±Ç, SCÆí, Á¦4È£,
pp. 254-262, 2002³â 7¿ù.
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[3] ¹®Á¤¿õ*,
¾çÈñ¼®*, À̽ÂÈÆ*, "»õ·Î¿î
±âÁØÀü¾Ð Àΰ¡¹æ¹ýÀ» »ç¿ëÇÏ´Â
8b 200MHz ½Ã°£°øÀ¯ ¼ºê·¹ÀΡ
ADC" ´ëÇÑÀüÀÚ°øÇÐȸ ³í¹®Áö,
Á¦39±Ç, SCÆí, Á¦4È£, pp. 263-273,
2002³â 7¿ù.
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[1] "¾¾¸ð½º ÁõÆø±âÀÇ ¹ÙÀ̾ ȸ·Î¿Í ±× ¾¾¸ð½º Æ®·£Áö½ºÅÍÀÇ
ä³Î±æÀÌ Á¶Á¤¹æ¹ý," ¹ß¸íÀÚ : À̰Áø, Ȳ¼º¿í, Àüº´·Ä, À̽ÂÈÆ*, ¿À´ëÀÏ, µî·ÏÀÏÀÚ : 2000. 6. 27, µî·Ï¹øÈ£
: 10-266719, µî·Ï±¹°¡ : Çѱ¹.
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[2] "½ÅÈ£ ó¸® ¼Óµµ°¡ °³¼±µÈ ÀÌÁß Ã¤³Î ±¸Á¶ÀÇ ¼ºê·¹ÀΡ
¾Æ³¯·Î±× µðÁöÅ» º¯È¯ÀåÄ¡," ¹ß¸íÀÚ : À̽ÂÈÆ*, ±èÁÖÇü, Ȳ¼º¿í, µî·ÏÀÏÀÚ : 2000. 9. 27, µî·Ï¹øÈ£ :
10-276208, µî·Ï±¹°¡ : Çѱ¹.
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[3] "¹ÝµµÃ¼ÁýÀûȸ·Î 10b 100MHz D/A º¯È¯±â
: 2000SG10b100M-DAC," ¹èÄ¡¼³°è±ÇÀÚ : À̽ÂÈÆ*, µî·ÏÀÏÀÚ : 2000. 11. 17, ¹èÄ¡¼³°è µî·Ï¹øÈ£
: 0001109, µî·Ï±¹°¡ : Çѱ¹.
|

|
[4] "ÀúÀü¾Ð ¾¾¸ð¿À½º ¿¬»ê ÁõÆø±â ȸ·Î ¹× ±×°ÍÀ» ±¸ºñÇÑ
»ùÇà ¾Øµå Ȧµå ȸ·Î," ¹ß¸íÀÚ : À嵿¿µ, ÀÌÀ¯¹Ì, À̽ÂÈÆ*, °±Ù¼ø, ÃÖÈñö, µî·ÏÀÏÀÚ : 2000. 12. 14, µî·Ï¹øÈ£
: 10-284024, µî·Ï±¹°¡ : Çѱ¹.
|

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[5] "¾Æ³¯·Î±×/µðÁöÅÐ º¯È¯È¸·Î
(ANALOG/DIGITAL CONVERTER)," ¹ß¸íÀÚ : À嵿¿µ, À̽ÂÈÆ*, ¹Ú½Â¿ì, ÀÌÀ翱, ¹Ú¿ëÀÎ, µî·ÏÀÏÀÚ : 2001. 1. 11, µî·Ï¹øÈ£ : 10-286322, µî·Ï±¹°¡
: Çѱ¹.
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[6]
"¹ÝµµÃ¼ÁýÀûȸ·Î 10b 120MHz
A/D º¯È¯±â: 2001SG10b120M-ADC,"
¹ß¸íÀÚ : À̽ÂÈÆ*, µî·ÏÀÏÀÚ :
2001³â 11¿ù 5ÀÏ, ¹èÄ¡¼³°è µî·Ï¹øÈ£
: Á¦ 0001241È£, µî·Ï±¹°¡ : Çѱ¹.
|

|
[7]
"¹ÝµµÃ¼ÁýÀûȸ·Î 8b 52MHz
A/D º¯È¯±â: 2001SG8b52M-ADC,"
¹ß¸íÀÚ : À̽ÂÈÆ*, µî·ÏÀÏÀÚ :
2001³â 12¿ù 24ÀÏ, ¹èÄ¡¼³°è µî·Ï¹øÈ£
: Á¦ 0001291È£, µî·Ï±¹°¡ : Çѱ¹.
|

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[8]
"¹ÝµµÃ¼ÁýÀûȸ·Î 10b 50MHz
A/D º¯È¯±â: 2001SG10b50M-ADC,"
¹ß¸íÀÚ : À̽ÂÈÆ*, µî·ÏÀÏÀÚ :
2001³â 12¿ù 24ÀÏ, ¹èÄ¡¼³°è µî·Ï¹øÈ£
: Á¦ 0001292È£, µî·Ï±¹°¡ : Çѱ¹.
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[1] È«¼®¿ë, ¹Ú¼ºÁÖ, Áö¿ë, À̽ÂÈÆ*, "°øÀ¯¸Þ¸ð¸®Çü ATM ´ÜÀ§½ºÀ§Ä¡ÀÇ
FPGA ±¸Çö ¹× Ư¼ººÐ¼®,"Á¦ 5 ȸ ¹ÝµµÃ¼ ¼³°è±³À°¼¾ÅÍ (IDEC) Multi-Project Chip (MPW) ¹ßǥȸ
³í¹®Áý, pp. 363-368, 1999³â 10¿ù.
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[2] Seung-Chul Lee*, Jin-Park,
Jin-Sik Yoon*, Jung-Hee Song, and Seung-Hoon Lee*, "A 3V 110mW 10b
100MS/s digital-to-analog converter," IDEC Conference 2000 Summer,
pp. 11-14, Aug. 2000.
|

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[3] Seung-Chul Lee*, Dong-Soo Park*,
Myung-Whan Choi, and Seung-Hoon Lee*, "A low- ripple
switched-capacitor DC-DC up converter for low-voltage applications,"
IDEC Conference 2000 Summer, pp. 3-6, Aug. 2000.
|

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[4] Jin-Sik Yoon*, Dong-Soo Park*,
Seung-Chul Lee*, Yong Jee, and Seung-Hoon Lee*, "An 800 MHz PLL with
intrinsic 50% duty cycle," IDEC Conference 2000 Summer, pp.
19-22, Aug. 2000.
|
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[5]
Seung-Hoon
Lee*, "°í¼Ó °íÇØ»óµµ µ¥ÀÌÅÍ
º¯È¯±â," ³»ÀåÇü½Ã½ºÅÛ ¼³°è¼¾ÅÍ
»êÇÐÄܼҽþö ÇмúȸÀÇ 2001,
¼¿ï´ëÇб³ ¹ÝµµÃ¼°øµ¿¿¬±¸¼Ò,
2001³â 12¿ù 13ÀÏ.
|

|
[6]
¹®Á¤¿õ*,
À¯»ó¹Î*, ¾çÈñ¼®*, À̽ÂÈÆ*, "´ÜÀÏ
Æú¸® µðÁöÅÐ °øÁ¤À» »ç¿ëÇÏ´Â
8b 200MHz ½Ã°£ °øÀ¯ ¼ºê·¹ÀΡ
ADC," Á¦ 9ȸ Çѱ¹ ¹ÝµµÃ¼
Çмú´ëȸ ³í¹®Áý, pp. 161-162,
2002³â 2¿ù.
|

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[7] ¿ÀÅÂȯ*, À±Áø½Ä*, À̽ÂÈÆ*, "ºñ³Ã°¢
Àû¿Ü¼± ¼¾¼ ¾î·¹À̸¦ À§ÇÑ CMOS
½ÅÈ£°ËÃâ ȸ·Î," Á¦ 9ȸ
Çѱ¹ ¹ÝµµÃ¼ Çмú´ëȸ ³í¹®Áý,
pp. 165-166, 2002³â 2¿ù.
|

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[8] ¹Úµ¿¼ö*,
¹ÚÁ¾¹ü*, À̽ÂÈÆ*, "°í¼Ó
È¥¼º¸ðµå ÁýÀûȸ·Î¸¦ À§ÇÑ ¿Â-Ĩ
CMOS Àü·ù ¹× Àü¾Ð ·¹ÆÛ·±½º ȸ·Î,"
Á¦ 9ȸ Çѱ¹ ¹ÝµµÃ¼ Çмú´ëȸ
³í¹®Áý, pp. 729-730, 2002³â
2¿ù.
|

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[9] Sang-Min
Yoo*, Tae-Hwan Oh*, Jeong-Woong
Moon*, Seung-Hoon Lee*, and
Unku Moon, "A 2.5V 10b
120MSample/s CMOS pipelined
ADC with high SFDR," ITRC
Forum 2002, May 2002.
|

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[10]
Young-Jae Cho*, Hyun-Hee
Bae, Yong Jee, and Seung-Hoon
Lee*, "On-Chip CMOS current
and voltage references for high-speed
mixed-mode integrated circuits,"
IDEC Conference 2002 Summer,
pp. 45-48, Aug. 2002.
|
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[1] "12 bit A/D º¯È¯±â ¼³°è ¹× ±â¼ú°³¹ß,"
Çö´ëÀüÀÚ(ÁÖ), 1Â÷³âµµ ÃÖÁ¾º¸°í¼, 1999³â 12¿ù.
|
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[2] "10 ºñÆ® 100Msps ¾Æ³¯·Î±×-µðÁöÅÐ ½ÅÈ£º¯È¯±â
±¸Á¶¿¬±¸," Çѱ¹ÀüÀÚÅë½Å¿¬±¸¿ø, 1Â÷³âµµ ÃÖÁ¾º¸°í¼, 1999³â 12¿ù.
|
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[3] "Clock, Àü¿ø, ¹× °í¼Ó ÀÎÅÍÆäÀ̽º ȸ·Î ±â¼ú
°³¹ß," 5Â÷³âµµ ÃÖÁ¾º¸°í¼, Åë»ó»ê¾÷ºÎ, Á¤º¸Åë½ÅºÎ, °úÇбâ¼úó, 2000³â 1¿ù.
|
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[4] "ºñ³Ã°¢ Àû¿Ü¼± ¼¾¼ ¾î·¹ÀÌÀÇ ½ÅÈ£ ó¸® ÀåÄ¡ÀÇ ¼³°è"
1Â÷³âµµ Áß°£º¸°í¼, ´ë¿ìÀüÀÚ, 2000³â 4¿ù.
|
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[5] "°íÇØ»óµµ/°í¼Ó ¾Æ³¯·Î±×-µðÁöÅÐ ½ÅÈ£º¯È¯±â
(A/D Converter) ¼³°è" 1Â÷³âµµ Áß°£º¸°í¼, Çѱ¹ÀüÀÚÅë½Å¿¬±¸¿ø, 2000³â 6¿ù.
|
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[6] "°íÇØ»óµµ/°í¼Ó ¾Æ³¯·Î±×-µðÁöÅÐ ½ÅÈ£º¯È¯±â
(A/D Converter) ¼³°è" 1Â÷³âµµ ÃÖÁ¾º¸°í¼, Çѱ¹ÀüÀÚÅë½Å¿¬±¸¿ø, 2000³â 8¿ù.
|
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[7] "ºñ³Ã°¢ Àû¿Ü¼± ¼¾¼ ¾î·¹ÀÌÀÇ ½ÅÈ£ ó¸® ÀåÄ¡ÀÇ ¼³°è"
1Â÷³âµµ ÃÖÁ¾º¸°í¼, ´ë¿ìÀüÀÚ(ÁÖ), 2001³â 3¿ù.
|
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[8] "»õ·Î¿î ÄÚµù±â¹ýÀ» »ç¿ëÇÑ 10b Ãʰí¼Ó CMOS
A/D º¯È¯±â ¼¿ °³¹ß" 1Â÷³âµµ Áß°£º¸°í¼, Çö´ëÀüÀÚ(ÁÖ), 2001³â 3¿ù.
|
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[9]
"An
8b 200 MHz 0.18 um CMOS A/D
Converter" Technical Report,
Silicon Image Inc. USA, 2001³â
5¿ù.
|
|
[10]
"»õ·Î¿î
ÄÚµù±â¹ýÀ» »ç¿ëÇÑ 10b Ãʰí¼Ó
CMOS A/D º¯È¯±â ¼¿ °³¹ß"
1Â÷³âµµ ÃÖÁ¾º¸°í¼, ÇÏÀ̴нº(ÁÖ),
2001³â 8¿ù.
|
|
[11]
"11
bits 70 MHz ADC °³¹ß" 1Â÷³âµµ
Áß°£º¸°í¼, (ÁÖ)½ºÅڽýºÅÚ·¹ÄÞ,
2001³â 8¿ù.
|
|
[12]
"Testability¸¦
°í·ÁÇÑ È¥¼º¸ðµåÁýÀûȸ·Î¿ë 10b
150MHz ADC IP °³¹ß," 1Â÷³âµµ
Áß°£º¸°í¼, »ï¼ºÀüÀÚ(ÁÖ), 2002³â
1¿ù.
|
|
[13]
"11
bits 70 MHz ADC °³¹ß" 1Â÷³âµµ
ÃÖÁ¾º¸°í¼, (ÁÖ)½ºÅڽýºÅÚ·¹ÄÞ,
2002³â 5¿ù.
|
|
[14]
"Testability¸¦
°í·ÁÇÑ È¥¼º¸ðµåÁýÀûȸ·Î¿ë 10b
150MHz ADC IP °³¹ß," 1Â÷³âµµ
ÃÖÁ¾º¸°í¼, »ï¼ºÀüÀÚ(ÁÖ), 2002³â
9¿ù.
|

|
[1] "CMOS ¾Æ³¯·Î±×/È¥¼º¸ðµå ÁýÀû½Ã½ºÅÛ ¼³°è (»ó),"
ÀÌ ½ÂÈÆ, ±è ¹ü¼·, ¼Û ¹Î±Ô, ÃÖ ÁßÈ£, ½Ã±×¸¶ÇÁ·¹½º, 1999³â 12¿ù.
|

|
[2] "CMOS ¾Æ³¯·Î±×/È¥¼º¸ðµå ÁýÀû½Ã½ºÅÛ ¼³°è (ÇÏ),"
ÀÌ ½ÂÈÆ, ±è ¹ü¼·, ¼Û ¹Î±Ô, ÃÖ ÁßÈ£, ½Ã±×¸¶ÇÁ·¹½º, 1999³â 12¿ù.
|
|
[1] Seung-Hoon Lee*, R&D
activities/consulting of ADC and DAC for Gigabit Ethernet chip, March
2000 - present, Silicon Image Inc., U. S. A.
(´ë»ó±¹°¡ : ¹Ì±¹, ´ë»ó±â°ü : ¹Ì±¹ Silicon Image, ¿¬¼ö±â°£ : 2000³â 7¿ù 20ÀϺÎÅÍ 2001³â 8¿ù 31ÀϱîÁö,
¸ñÀû : R&D activities/consulting of ADC and DAC for Gigabit Ethernet
chip, ¿¬¼ö³»¿ë : ¿¬±¸°³¹ß ÁøÇà Áß, ¿¬¼öÀÚ ¼±¹ß±âÁØ : ¿¬±¸Ã¥ÀÓÀÚ, ´ë»ó±â°ü Çù·Â»çÀ¯ : ±³¼ö¿Í Çù·Â±â°ü
|
|
[2] Young-Deuk Jeon*, Byeong-Lyeol
Jeon, Seung-Chul Lee*, Sang-Min Yoo*, and Seung-Hoon Lee*, "A 12b 50
MHz 3.3 V CMOS Acquisition Time Minimized A/D Converter," ASP-DAC
2000 (Asia and South Pacific Design Automation Conference 2000),
Japan, pp. 613-616, Jan. 2000.
(´ë»ó±¹°¡ : ÀϺ», ´ë»ó±â°ü : ASP-DAC 2000 (Asia and South Pacific Design Automation
Conference 2000), ¿¬¼ö±â°£ : 2000³â 1¿ù 25ÀÏ - 1¿ù 29ÀÏ (5Àϰ£), ¸ñÀû : ÇÐȸ ³í¹®¹ßÇ¥, ÀÚ·á¼öÁý ¹×
±¹Á¦ °æÇèÃàÀû, Âü¿©ÀÚ : Àü ¿µµæ, ÀÌ ½Âö, ÀÌ ½ÂÈÆ, ¿¬¼ö³»¿ë : ±¹Á¦³í¹® ¹ßÇ¥, ¿¬¼öÀÚ ¼±¹ß±âÁØ ¹× ¹æ¹ý : ³í¹®¹ßÇ¥ÀÚ Áß ±â¿©µµ°¡
³ôÀº 2ÀÎÀ» ¼±¹ßÇÔ, ´ë»ó±â°ü (ÇÐȸ) ¼±Á¤»çÀ¯ : IEEE°¡ Áö¿øÇÏ´Â ¼öÁØ ±ÞÀÇ ±¹Á¦ÇÐȸÀÓÀ» °í·ÁÇÔ.)
|
|
[3] Young-Deuk Jeon*, Joon-Seok Lee*, Seung-Chul
Lee*, Sang-Min Yoo*, and Seung-Hoon Lee*, "Acquisition- time minimization and merged-capacitor switching
techniques for sampling-rate and resolution improvement of CMOS
ADCs," ISCAS (Intl. Sym. on Circuits and Syst.) 2000, Geneva,
pp. III 451-454, Switzerland, May 2000
(´ë»ó±¹°¡ : ½ºÀ§½º Á¦³×¹Ù, ´ë»ó±â°ü : ISCAS (Intl. Sym. on Circuits and Syst.) 2000, ¿¬¼ö±â°£
: 2000³â 5¿ù 27ÀÏ - 6¿ù 1ÀÏ (5¹Ú 6Àϰ£), ¸ñÀû : ÇÐȸ ³í¹®¹ßÇ¥, ÀÚ·á¼öÁý ¹× ±¹Á¦ °æÇèÃàÀû, Âü¿©ÀÚ : ÀÌ ½Âö,
À¯ »ó¹Î, ÀÌ ½ÂÈÆ, ¿¬¼ö³»¿ë : ±¹Á¦³í¹® ¹ßÇ¥, ¿¬¼öÀÚ ¼±¹ß±âÁØ ¹× ¹æ¹ý : ³í¹®¹ßÇ¥ÀÚ
Áß ±â¿©µµ°¡ ³ôÀº 2ÀÎÀ» ¼±¹ßÇÔ, ´ë»ó±â°ü (ÇÐȸ) ¼±Á¤»çÀ¯ : IEEE°¡ Áö¿øÇÏ´Â ¼öÁØ ±ÞÀÇ ±¹Á¦ÇÐȸÀÓÀ» °í·ÁÇÔ.)
|
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[4] Seung-Hoon Lee*, Sang-Min Yoo*, Tae-Hwan Oh*,
Jeong-Woong Moon*, Jin-Shik Yoon*, ISSCC 2001 (International Solid
State Circuits Conference 2001) ±¹Á¦ÇÐȸ Âü°¡ ¹× ¹Ì±¹ ½Ç¸®Äܹ븮 ½ÃÂû, San Francisco,
California, USA. (´ë»ó±¹°¡ : ¹Ì±¹, ´ë»ó±â°ü :
ISSCC ÇÐȸ ¹× ¹Ì±¹ Silicon Image Inc. µî º¥Ã³¾÷ü, ±â°£ : 2001³â 2¿ù 4ÀÏ - 2¿ù 10ÀÏ, ¸ñÀû ¹× ³»¿ë
: ÇÐȸÂü¼® ¹× Silicon Image Inc. µî ¹Ì±¹ º¥Ã³È¸»ç ½ÃÂû, ¿¬¼öÀÚ ¼±¹ß±âÁØ ¹× ¹æ¹ý : ¿¬±¸½Ç¿¡¼ ¿¬±¸°³¹ß ±â¿©°¡ Å«
¼ø¼ÀÌµÇ ±âÁ¸¿¡ ÇØ¿Ü °æÇèÀÌ ÀûÀº ÀÚ ¼ø¼·Î ¼±Á¤, ´ë»ó±â°ü ¼±Á¤ »çÀ¯ : ISSCC2001Àº ȸ·Î ¼³°èÀÇ ¼¼°è ÃÖ´ë ÇÐȸÀ̸ç, ½Ç¸®Äܹ븮
½ÃÂûÀº ¿¬±¸Ã¥ÀÓÀÚ°¡ ¾È½Ä³â ¿¬±¸¸¦ ÇÑ Silicon Image Inc.¸¦ Áß½ÉÀ¸·Î ½ÃÂûÀ» ÁÖµµÇÏ¿´À½)
|
|
[5]
À̽ÂÈÆ*,
¹ÚÁ¾¹ü*, CICC2002
(Custom Integrated Circuits
Conference 2002) ±¹Á¦ÇÐȸ
Âü°¡ ¹× ÁÖ¿ä ±â¼ú³í¹® ¹ßÇ¥,
Orlando, Florida, USA. (´ë»ó±¹°¡
: ¹Ì±¹, ´ë»ó±â°ü : CICC2002
ÇÐȸ, ±â°£ : 2002³â 5¿ù 11ÀÏ
- 5¿ù 17ÀÏ, ¸ñÀû ¹× ³»¿ë : ÇÐȸÂü¼®
¹× ³í¹®¹ßÇ¥, ¿¬¼öÀÚ ¼±¹ß±âÁØ
¹× ¹æ¹ý : ¿¬±¸½Ç¿¡¼ ¿¬±¸°³¹ß
±â¿©µµ°¡ Å« ¼ø¼ÀÌµÇ ±âÁ¸¿¡
ÇØ¿Ü °æÇèÀÌ ÀûÀº ÀÚ ¼ø¼·Î ¼±Á¤,
´ë»ó±â°ü ¼±Á¤ »çÀ¯ : CICC2002´Â
ȸ·Î ¼³°èÀÇ ¼¼°è ÃÖ°íÇÐȸ ÁßÀÇ
ÇϳªÀÓ)
|
|
[6]
À̽ÂÈÆ*,
¹ÚÁ¾¹ü*, ¾çÈñ¼®*, ¹èÇöÈñ*,
Á¶¿µÀç*, ITC-CSCC2002
(International Technical Conference
on Circuits/Systems, Computers
and Communications 2002)
±¹Á¦ÇÐȸ Âü°¡ Keynote Speech
(±âÁ¶¿¬¼³), Phuket, Thailand.
(´ë»ó±¹°¡ : ű¹, ´ë»ó±â°ü
: ITC-CSCC 2002 ÇÐȸ, ±â°£ :
2002³â 7¿ù 16ÀÏ - 7¿ù 20ÀÏ,
¸ñÀû ¹× ³»¿ë : ÇÐȸÂü¼® ¹× Keynote
Speech ±âÁ¶¿¬¼³ ³í¹®¹ßÇ¥, ¿¬¼öÀÚ
¼±¹ß±âÁØ ¹× ¹æ¹ý : ¿¬±¸½Ç¿¡¼
¿¬±¸°³¹ß ±â¿©µµ°¡ Å« ¼ø¼À̵Ç
±âÁ¸¿¡ ÇØ¿Ü °æÇèÀÌ ÀûÀº ÀÚ ¼ø¼·Î
¼±Á¤, ´ë»ó±â°ü ¼±Á¤ »çÀ¯ : ITC-CSCC
2002¿¡¼ ÃÊû¹ÞÀ½)
|

|
[1] You-Jin Cha* (¼®»ç : 2000. 2. Á¹¾÷),
Seung-Hoon Lee*, and Jin-Kug Lee, "Digitally-controlled automatic
gain control circuits for CMOS CCD camera interface," IEE
Electronics Letters, vol. 35, no, 22, pp. 1909-1910, Oct. 1999. [SCI]
|

|
[2] Young-Deuk Jeon* (¼®»ç : 2000. 2. Á¹¾÷),
and Seung-Hoon Lee*, "Acquisition time minimization techniques for
high-speed analog signal processing," IEE Electronics Letters,
vol. 35, no. 23, pp. 1990-1991, Nov. 1999. [SCI]
|

|
[3] Jin Park (¼®»ç : 1999. 8. Á¹¾÷),
Seung-Chul Lee* (¼®»ç : 2000. 8. Á¹¾÷), and Seung-Hoon Lee*, "3 V 10b 70
MHz CMOS D/A converter for video applications," IEE Electronics
Letters, vol. 35, no. 24, pp. 2071-2073, Nov. 1999. [SCI]
|

|
[4] Tae-Hwan Oh* (¼®»ç 3Çбâ) and
Seung-Hoon Lee*, "Single-chip CMOS CCD camera interface based on
digitally-controlled capacitor- segment combination," IEEE Trans.
on Circuits Syst. II, vol. 47, no. 11, pp. 1338-1343, Nov. 2000.
[SCI]
|

|
[5] Jin Park (¼®»ç : 1999. 8 Á¹¾÷),
Seung-Chul Lee* (¼®»ç : 2000. 8 Á¹¾÷), Jin-Sik Yoon* (¼®»ç 3Çбâ), and Seung-Hoon
Lee*, "A 3V 10b 100MS/s digital-to-analog converter for cable modem
applications," IEEE Trans. on Consumer Electronics, vol. 46,
no, 4, pp. 1043-1047, Nov. 2000. [SCI]
|

|
[6] Seung-Ho Lee* (¼®»ç : 2000. 2 Á¹¾÷),
Jung-Woong Moon* (¼®»ç 3Çбâ), and Seung-Hoon Lee*, "An 8b 52MHz
double-channel CMOS subranging A/D converter for DSL applications,"
IEICE Trans. on Electronics, vol. E84-C, no. 4, April 2001. [SCI]
|

|
[7]
Joon-Seok Lee* (¼®»ç : 2000.
2 Á¹¾÷), "Comments on comments
on interstage gain- proration
technique for digital-domain
multistep ADC calibration,"
IEEE
Trans.
Circuits Syst. II, Vol 48, No.
7, pp. 745-749, July 2001. [SCI]
|

|
[8]
Joon-Seok Lee* (¼®»ç : 2000.
2 Á¹¾÷), "Resolution enhancement
techniques for high-speed multi-stage
pipelined ADC's based on a multi-bit
multiplying DAC," IEICE
Trans. on Electronics,
vol. E84-C, No. 8, pp. 1092-1099,
Aug. 2001. [SCI]
|

|
[9]
Seung-Chul Lee* (¼®»ç : 2000.
8 Á¹¾÷), "A Low-Ripple
Switched-Capacitor DC-DC up
Converter for Low-Voltage Applications,"
IEICE Trans. on Electronics,
vol. E84-C, No. 8, pp. 1100-1103,
Aug. 2001. [SCI]
|
|
[10]
Jung-Woong Moon* (¼®»ç 2002.
2 Á¹¾÷), "An 8b 200MHz
Time-Interleaved Subranging
ADC Based on a Single-Poly Digital
CMOS Process," IEICE
Trans. on Electronics,
Jan. 2003 to be published. [SCI]
|
¡ÜƯÇãÃâ¿ø³»¿ë

|
[1] "½ºÀ§Ä¡µå Ä¿ÆÐ½ÃÅÍ È¸·Î¿¡¼ Á¤Âø½Ã°£À» ÃÖ¼ÒÈÇÑ ¹ÙÀ̾
ȸ·Î ¹× ±×¸¦ ±¸ºñÇÑ ÁõÆøÀåÄ¡," Ãâ¿øÀÏÀÚ : 1999. 10. 30, Ãâ¿ø¹øÈ£ : 1999-47733, Ãâ¿ø±¹°¡ : Çѱ¹.
|

|
[2] "Gain Controller Using
Switched Capacitors," Application Date : 2000. 5. 23, Application
Number : 09/575994, Filing Country : US.
|

|
[3] "ÆÄÀÌÇÁ¶óÀÎ ¾Æ³¯·Î±×/µðÁöÅÐ º¯È¯±âÀÇ º´ÇÕ Ä³ÆÐ½ÃÅÍ
½ºÀ§Äª ±¸Á¶," Ãâ¿øÀÏÀÚ : 2000. 11. 28, Ãâ¿ø¹øÈ£ : Á¦ 10-2000-0071360È£, Ãâ¿ø±¹°¡ : Çѱ¹.
|
¡Ü±×¿Ü/ÃßÁø»çÇ×
½ÇÀû
|
[1] Àü¿µµæ* (¼®»ç°úÁ¤), "CMOS A/D º¯È¯±âÀÇ »ùÇøµ ¼Óµµ
¹× ÇØ»óµµ Çâ»óÀ» À§ÇÑ Á¤Âø½Ã°£ ÃÖ¼ÒÈ ¹× º´ÇÕ Ä³ÆÐ½ÃÅÍ ½ºÀ§Äª ±â¹ý", 1999³âµµ IEEE Çлý³í¹® CONTEST ³í¹®Áý,
pp. 59-63, 1999.12.04, ´Ü±¹´ëÇб³ »ç¹üÇаü, ÃÖ¿ì¼ö»ó ¼ö»ó, IEEE Korea Council, Á¤ÅëºÎ, Á¤º¸Åë½Å¿¬±¸ÁøÈï¿ø.
|
|
[2] Àü ¿µµæ* (¼®»ç°úÁ¤), ASP-DAC 2000 Travel Grant
Award, US$300, Best Paper Candidates, Jan. 2000, Yokohama, Japan.
|
|
[3] ÀÌ ½ÂÈÆ* ±³¼ö, IDEC ¿ì¼ö Working Group »ó ¼ö»ó, ¹ÝµµÃ¼¼³°è±³À°¼¾ÅÍ
(IDEC), 2000³â 2¿ù 24ÀÏ.
|
|
[4] Àü ¿µµæ* (¼®»ç°úÁ¤), "Acquisition-time
minimization and merged-capacitor switching techniques for sampling-rate
and resolution improvement of CMOS ADCs", Á¦ 6 ȸ »ï¼ºÀüÀÚ ÈÞ¸ÕÅ×Å© ³í¹®´ë»ó, 2000³â
2¿ù 29ÀÏ, »ï¼º»ý¸íºôµù 1Ãþ CINEX Ȧ, Àå·Á»ó ¼ö»ó, »ï¼ºÀüÀÚ(ÁÖ) ÈÄ¿ø.
|
|
[5] ÀÌ ½ÂÈÆ* ±³¼ö, "CMOS È¥¼º¸ðµå ÁýÀû½Ã½ºÅÛ ½Ç½À,"
¹ÝµµÃ¼¼³°è±³À°¼¾ÅÍ ±¤¿î´ë Áö¿ª¼¾ÅÍ (IDEC) 1999³âµµ ±â¾÷ü ¹× °¢±Þ ´ëÇб³ ´ë»ó ȸ·Î ¼³°è Ư°, 1999.10.4 -
10.7.
|
|
[6] ÀÌ ½ÂÈÆ* ±³¼ö, "CMOS È¥¼º¸ðµå ÁýÀû½Ã½ºÅÛ ¼³°è ¹× ½Ç½À,"
±âÈï »ï¼ºÀüÀÚ ¹ÝµµÃ¼ÃѰý ¿¬¼ö½Ç, 1999³âµµ ±â¾÷ü ´ë»ó ȸ·Î ¼³°è ÃâÀå °ÀÇ, 1999.11.8 - 11.11.
|
|
[7] ÀÌ ½ÂÈÆ* ±³¼ö, "¾Æ³¯·Î±× ASIC ÀÇ ÇØ¼® ¹× ¼³°è,"
Çѱ¹°úÇпø ¹ÝµµÃ¼ ¼³°è±³À°¼¾ÅÍ (IDEC) 1999³âµµ ±â¾÷ü ¹× °¢±Þ
´ëÇб³ ´ë»ó ÁßÀå±â ȸ·Î ¼³°è ¹× ÇØ¼® Ư°, 1999. 9 -2000. 1.
|
|
[8] ÀÌ ½ÂÈÆ* ±³¼ö, "CMOS È¥¼º¸ðµå IC ¼³°è ¹× ½Ç½À,"
¹ÝµµÃ¼¼³°è±³À°¼¾ÅÍ ±¤¿î´ë Áö¿ª¼¾ÅÍ (IDEC) 2000³âµµ ±â¾÷ü ¹× °¢±Þ ´ëÇб³ ´ë»ó ȸ·Î ¼³°è Ư°, 2000. 2. 21 -
24.
|
|
[9] À̽ÂÈÆ* ±³¼ö, "Device/Circuit Design
for High Performance VLSI: Design of high performance/low power data
converters ," ISRC (¼¿ï´ë ¹ÝµµÃ¼ °øµ¿¿¬±¸¼Ò) 2000³âµµ ȸ·Î¼³°è Ư°, 2000.7.3-7.5.
|
|
[10] À̽ÂÈÆ* ±³¼ö, Çѱ¹°úÇпø ¹ÝµµÃ¼ ¼³°è±³À°¼¾ÅÍ (IDEC) Àü¹®À§¿ø
1999³â 5¿ù - 2000³â 4¿ù.
|
|
[11] À̽ÂÈÆ* ±³¼ö, Çѱ¹¹ÝµµÃ¼ »ê¾÷Çùȸ ǥâÀå ¼ö»ó, HDTV¿ë
"ÁÖ¹®Çü ¹ÝµµÃ¼ °³¹ß»ç¾÷", 2000³â 8¿ù 10ÀÏ.
|
|
[12] Joon-Seok Lee* and Seung-Chul Lee*,
"Acquisition-time minimization and merged capacitor switching
techniques for sampling-rate and resolution improvement of CMOS
ADCs", Second Place Award in the 1999 Region 10 IEEE Postgraduate
Student Paper Competition, IEEE, Oct. 2000.
|
¡Ü±âŸ¿¬±¸½ÇÀû
BK21°ü·Ã»ç¾÷
±³À°¼º°ú

1) - ° Á ¸í :
|
ÀüÀÚȸ·Î¥± °ÀÇ °èȹ¼
|
- °³¼³¿¬¿ù :
|
1999³â 2Çбâ
|
- °Àǰ³¿ä :
|
¸Þ¸ð¸®, ¸¶ÀÌÅ©·Î
ÇÁ·Î¼¼¼, DSP, Åë½Å ½Ã½ºÅÛ, ºñ¸Þ¸ð¸® ASIC µî, Çö´ëÀÇ Ã·´Ü Á¤º¸±â¼ú ºÐ¾ß¿¡ ÇʼöÀûÀÎ ´Ù¾çÇÑ ÀüÀÚ°øÇÐ °ú¸ñµé ÁßÀÇ Çϳª·Î¼,
ÀüÀÚȸ·Î I ¿¡¼ ¹è¿î ´ÙÀÌ¿Àµå ¹× Æ®·£Áö½ºÅÍ¿Í °°Àº ´Éµ¿ ¼ÒÀÚµéÀ» »ç¿ëÇÏ¿©, ´ëÇ¥ÀûÀÎ ÀÀ¿ëȸ·ÎÀÎ Â÷µ¿ ÁõÆø±â ¹× ´Ù´Ü ÁõÆø±âÀÇ ÇØ¼®,
³ôÀº Á֯ļö ¿µ¿ª¿¡¼ÀÇ Á֯ļö Ư¼º ºÐ¼®, ±Ëȯ ȸ·Î ÀÌ·Ð µîÀ» °øºÎÇϸç, ÀÌ·¯ÇÑ ±âº» ºí·°µéÀ» »ç¿ëÇÏ´Â ´ë±Ô¸ð ¾Æ³¯·Î±×/µðÁöÅ» ÁýÀû
ȸ·ÎÀÇ ÇØ¼® ¹× ¼³°è »ç·Ê µîÀ» ´Ù·é´Ù.
|
|
|
2) - ° Á ¸í :
|
ÀüÀÚȸ·Î I °ÀÇ °èȹ¼
|
- °³¼³¿¬¿ù :
|
2000³â 1Çбâ
|
- °Àǰ³¿ä :
|
°íºÎ°¡°¡Ä¡¸¦ Áö´Ñ Çö´ëÀÇ Ã·´Ü ¹ÝµµÃ¼ ȸ·Î
¹× ½Ã½ºÅÛ ÀüÀÚ »ê¾÷¿¡ ÇʼöÀûÀÎ ´Ù¾çÇÑ ÀüÀÚ°øÇÐ °ú¸ñÀÇ ¼±¼ö°ú¸ñ ÁßÀÇ Çϳª·Î¼, °¡Àå ±âº»ÀûÀÎ ´Éµ¿ ÀüÀÚ¼ÒÀڷμÀÇ
´ÙÀÌ¿Àµå (diode), ¹ÙÀÌÆú¶ó Æ®·£Áö½ºÅÍ (bipolar junction
transistor), MOSFET µîÀÇ µ¿ÀÛ¿ø¸® ¹× Ư¼ºÀ» ¹è¿ì¸ç, ÀÌ ´Éµ¿¼ÒÀÚ¸¦ ÀÌ¿ëÇÑ ±âº»ÀûÀÎ µ¿ÀÛ ºí·°À¸·Î¼ ¹ÙÀ̾ ȸ·Î,
ÁõÆø±â µîÀÇ ÇØ¼® ¹× ¼³°è ±â¹ý µîÀ» ´Ù·é´Ù
|
|
|
3) - ° Á ¸í :
|
ÀüÀÚȸ·Î I °ÀÇ °èȹ¼
|
- °³¼³¿¬¿ù :
|
2001³â 1Çбâ
|
- °Àǰ³¿ä :
|
Çö´ëÀÇ Ã·´Ü ¹ÝµµÃ¼ ¹×
½Ã½ºÅÛ ÀüÀÚ»ê¾÷¿¡ ÇÊ¿äÇÑ ´Ù¾çÇÑ ÀüÀÚ°øÇÐ °ú¸ñÀÇ ¼±¼ö°ú¸ñ ÁßÀÇ Çϳª·Î¼, °¡Àå ±âº»ÀûÀÎ ´Éµ¿ ÀüÀÚ¼ÒÀڷμÀÇ
´ÙÀÌ¿Àµå (diode), ¹ÙÀÌÆú¶ó Æ®·£Áö½ºÅÍ (bipolar junction transistor), MOSFET µîÀÇ µ¿ÀÛ¿ø¸® ¹× Ư¼ºÀ»
¹è¿ì¸ç, ÀÌ ´Éµ¿¼ÒÀÚ¸¦ ÀÌ¿ëÇÑ ±âº»ÀûÀÎ µ¿ÀÛ ºí·°À¸·Î¼ ¹ÙÀ̾ ȸ·Î, ÁõÆø±â µîÀÇ ÇØ¼® ¹× ¼³°è ±â¹ý µîÀ» ´Ù·é´Ù.
|
|
|
4) - ° Á ¸í :
|
ÀüÀÚȸ·Î II °ÀÇ °èȹ¼
|
- °³¼³¿¬¿ù :
|
2001³â 2Çбâ
|
- °Àǰ³¿ä :
|
¸Þ¸ð¸®,
¸¶ÀÌÅ©·Î ÇÁ·Î¼¼¼, DSP, Åë½Å
½Ã½ºÅÛ, ºñ¸Þ¸ð¸® ASIC µî, Çö´ëÀÇ
÷´Ü Á¤º¸±â¼ú ºÐ¾ß¿¡ ÇʼöÀûÀÎ
´Ù¾çÇÑ ÀüÀÚ°øÇÐ °ú¸ñµé ÁßÀÇ
Çϳª·Î¼, ÀüÀÚȸ·Î I ¿¡¼ ¹è¿î
´ÙÀÌ¿Àµå ¹× Æ®·£Áö½ºÅÍ¿Í °°Àº
´Éµ¿ ¼ÒÀÚµé ¹× R, L, C µî ¼öµ¿¼ÒÀÚµéÀ»
»ç¿ëÇÏ¿©, ´ëÇ¥ÀûÀÎ ÀÀ¿ëȸ·ÎÀÎ
Â÷µ¿ ÁõÆø±â (differential amplifier)
¹× ´Ù´Ü ÁõÆø±â (multi-stage
amplifier)ÀÇ ÇØ¼®, ³ôÀº Á֯ļö
¿µ¿ª¿¡¼ÀÇ Á֯ļö Ư¼º ºÐ¼®,
±Ëȯ ȸ·Î (feedback circuit)
ÀÌ·Ð µîÀ» °øºÎÇϸç, ÀÌ·¯ÇÑ ±âº»
ºí·ÏµéÀ» »ç¿ëÇÏ´Â ´ë±Ô¸ð ¾Æ³¯·Î±×/µðÁöÅÐ
ÁýÀû ȸ·Î (Integrated Circuits)ÀÇ
ÇØ¼® ¹× ¼³°è»ç·Ê µîÀ» ´Ù·é´Ù.
|
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5) - ° Á ¸í :
|
ÀüÀÚȸ·Î I °ÀÇ °èȹ¼
|
- °³¼³¿¬¿ù :
|
2002³â 1Çбâ
|
- °Àǰ³¿ä :
|
Çö´ëÀÇ
÷´Ü ¹ÝµµÃ¼ ¹× ½Ã½ºÅÛ ÀüÀÚ»ê¾÷¿¡
ÇÊ¿äÇÑ ´Ù¾çÇÑ ÀüÀÚ°øÇÐ °ú¸ñÀÇ
¼±¼ö°ú¸ñ ÁßÀÇ Çϳª·Î¼, °¡Àå
±âº»ÀûÀÎ ´Éµ¿ ÀüÀÚ¼ÒÀڷμÀÇ
´ÙÀÌ¿Àµå (diode), ¹ÙÀÌÆú¶ó Æ®·£Áö½ºÅÍ
(bipolar junction transistor),
MOSFET µîÀÇ µ¿ÀÛ¿ø¸® ¹× Ư¼ºÀ»
¹è¿ì¸ç, ÀÌ ´Éµ¿¼ÒÀÚ¸¦ ÀÌ¿ëÇÑ
±âº»ÀûÀÎ µ¿ÀÛ ºí·°À¸·Î¼ ¹ÙÀ̾
ȸ·Î, ÁõÆø±â µîÀÇ ÇØ¼® ¹× ¼³°è
±â¹ý µîÀ» ´Ù·é´Ù.
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