International Journal Paper / International Conference Paper

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International Conference Paper

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[1] S.H. Lee and B.S. Song, "A code-error calibrated two-step A/D converter," IEEE International Solid-State Circuits Conference (ISSCC), pp. 38-39, Feb. 1992.

 

[2] C. Mangelsdorf, S.H. Lee, M. Martin, H. Malik, T. Fukuda, and H. Matsumoto, "Design for testability in digitally-corrected ADCs," IEEE International Solid-State Circuits Conference (ISSCC), pp. 70-71, Feb. 1993. 

 

[3] C. Mangelsdorf, H. Malik, S.H. Lee, S. Hisano, and M. Martin, "A two-residue architecture for multistage ADCs," IEEE International Solid-State Circuits Conference (ISSCC), pp. 64-65, Feb. 1993. 

 

[4] S.H. Lee and B.S. Song, "Simplified digital calibration for multi-stage analog-to-digital converters," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1216-1219, May 1993. 

 

[5] S.H. Lee, "A pipelined A/D converter architecture for high linearity and high yield," Joint Technical Conference on Circuits Systems, Computers and Communications (JTC-CSCC), pp. 1102-1107, July 1994.

 

[6] H.C. Choi, S.H. Lee, S.Y. Hwang, G.S. Kang, S.H. Lee, and M.J. Choe, "A 10-bit 20-MHz three-stage A/D converter," International Conference on VLSI and CAD, pp. 139-142, Oct. 1995. 

 

[7] S.H. Lee, and S.Y. Hwang, "A 12b 10MHz 250mW CMOS A/D converter," IEEE International Solid-State Circuits Conference (ISSCC), pp. 316-317, Feb. 1996. 

 

[8] D.Y. Chang, K.J. Lee, S.Y. Hwang, and S.H. Lee, "A low-voltage current reference and its application to a 3V 10b 20MHz CMOS ADC," InternationalTechnical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), pp. 617-620, Okinawa, Japan, July. 14-16, 1997. 

 

[9] D.Y. Chang, J.Y. Lee, J.K. Lee, Y.I. Park, C. An, and S.H. Lee, "Design Techniques for a low-cost algorithmic A/D converter," International Conference on VLSI and CAD, pp. 427-429, Seoul, Korea, Oct. 13-15, 1997.

 

[10] B. L. Jeon, K. J. Lee, S. H. Lee, and S. W. Yoon, "A 10b 50MHz CMOS A/D converter for high-speed video applications," Asia and South Pacific Design Automation Conference (ASP-DAC), University Design Contest, Wanchai, Hong Kong, pp. 29-32, Jan. 18-21, 1999.

  

[11] J. K. Lee, D.Y. Chang, G. S. Kang, and S. H. Lee, "A single-chip CMOS CCD camera interface circuit with digitally controlled AGC," Asia and South Pacific Design Automation Conference (ASP-DAC), University Design Contest, Wanchai, Hong Kong, pp. 45-48, Jan. 18-21, 1999.

 

[12] J. K. Lee, D.Y. Chang, G. S. Kang, and S. H. Lee, "A single-chip CMOS CCD camera interface circuit with digitally controlled AGC," Asia and South Pacific Design Automation Conference (ASP-DAC), University Design Contest, Wanchai, Hong Kong, pp. 273-276, Jan. 18-21, 1999.

 

[13] J. H. Kim, S. W. Hwang, S. H. Lee, and Y. Jee, "An 8b 52MHz double-channel CMOS A/D converter for high-speed data communications," Asia and South Pacific Design Automation Conference (ASP-DAC), University Design Contest, Wanchai, Hong Kong, pp. 25-28, Jan. 18-21, 1999.

 

[14] J. Park, Y.J. Cho, S.C. Lee, and S.H. Lee, "A 3 V 10b 70 MHz digital-to-analog converter for video applications," IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), pp. 186-189, Aug. 23-25, 1999, Seoul, Korea.

 

[15] Y.J. Cha, J.K. Lee, J. Park, and S.H. Lee, "Digitally-controlled automatic gain control circuits for CMOS CCD electronic cameras," International Conference on VLSI and CAD, Oct. 26-27, pp. 342-345, 1999, Seoul, Korea.

 

[16] S.C. Lee, S. H. Lee, J. S. Lee, and S.H. Lee, "A 3 V 200 MHz PLL with a low-noise VCO based on a power-efficient low-ripple DC-DC converter," International Conference on VLSI and CAD, Oct. 26-27, pp. 346-348, 1999, Seoul, Korea.

 

[17] Y. D. Jeon, B. L. Jeon, S. C. Lee, S. M. Yoo, and S. H. Lee, "A 12b 50 MHz 3.3 V CMOS acquisition time minimized A/D converter," Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 613-616, Jan. 2000, Yokohama, Japan.

 

[18] Y. D. Jeon, J. S. Lee, S. C. Lee, S. M. Yoo, and S. H. Lee, "Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs," IEEE International Symposium on Circuits and Systems (ISCAS), pp. III 451-III 454, May 2000, Geneva, Switzerland.

 

[19] S. C. Lee, D. S. Park, J. H. Song, M. W. Choi, and S. H. Lee, "A low-ripple switched-capacitor DC-DC up converter for low-voltage applications," IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), Korea, pp. 13-16, Aug. 2000.

 

[20] S. C. Lee, J. Park, J. S. Yoon, J. H. Song, and S. H. Lee, "A 3V 10b 100MS/s digital-to-analog converter for cable modem applications," IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), Korea, pp. 203-205, Aug. 2000.

 

[21] S.M. Yoo, T.H. Oh, J.W. Moon, S.H. Lee, and U. Moon, "A 2.5V 10b 120MSample/s CMOS pipelined ADC with high SFDR," IEEE Custom Integrated Circuits Conference (CICC), Orlando, Florida, pp. 441-444, May 2002.

 

[22] Seung-Hoon Lee (Keynote Speech), "8b-12b 50-200MS/s low-power pipelined ADC design techniques for SoC applications," InternationalTechnical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Phuket, Thailand, Aug. 2002.

 

[23] Seung-Hoon Lee, "An 11b 70MHz 1.2mm2 49mW 0.18um CMOS ADC with on-chip current/voltage references," European Solid-State Circuits Conference (ESSCIRC) 2002, Florence, Italy, pp. 463-466, Sept. 2002.

 

[24] Sang-Min Yoo, Jong-Bum Park, Hee-Suk Yang, Hyuen-Hee Bae, K. H. Moon, H. J. Park, S.H. Lee, and J. H. Kim, "A 10b 150MS/s 123mW 0.18um CMOS Pipelined ADC," IEEE International Solid-State Circuits Conference (ISSCC), pp. 326-327, Feb. 2003.

 

[25] Hyuen-Hee Bae, Jin-Sik Yoon, Myung-Jin Lee, Eun-Seok Shin, and Seung-Hoon Lee, "A 3V 12b 100 MS/s CMOS D/A converter for high-speed system applications," IEEE International Symposium on Circuits and Systems (ISCAS), pp. Ⅰ869-Ⅰ872 , May 2003.

 

[26] Young-Jae Cho, Hyuen-Hee Bae, Myung-Jin Lee, Seung-Hoon Lee, and Young-Lok Kim, "An 8b 220MS/s 0.25um CMOS pipeline ADC with on-chip RC-filter based voltage references," IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC), Fukuoka, Japan, pp. 90-93, Aug. 2004.

 

[27] Myung-Jin Lee, Young-Jae Cho, Woo-Jin Bae, and Seung-Hoon Lee, "8b 200 MS/s 0.25 um CMOS A/D Converters with 500 MHz Input Bandwidth," International SoC Design Conference (ISOCC), pp. 660-661, Oct. 2004.

 

[28] Se-Won Kim, Young-Jae Cho, Kyung-Hoon Lee, Seung-Hoon Lee, Jae-Yup Lee, Hyun-Chul Noh, and Hee-sub Lee, "An 8b 240 MS/s 1.36 mm2 104 mW 0.18 um CMOS ADC for DVDs with Dual-Mode Inputs," IEEE International Symposium on Circuits and Systems (ISCAS), pp. 4054-4057, May 2005.

 

[29] Seung-Chul Lee, Gyu-Hyun Kim, Jong-Kee Kwon, Jong-Dae Kim, and Seung-Hoon Lee, "Offset and Dynamic Gain-Mismatch Reduction Techniques for 10b 200MS/s Parallel Pipeline ADCs," European Solid-State Circuits Conference (ESSCIRC), Grenoble, France, pp. 531-534, Sept. 2005.

 

[30] Byoung-Han Min, Hee-Sung Chae, Hee-Won Park, and Seung-Hoon Lee, "A 10b 100 MS/s 1.4 mm2 56 mW 0.18 um CMOS A/D Converter with 3-D Fully Symmetrical Capacitors," International SoC Design Conference (ISOCC), pp. 324-327, Oct. 2005.

 

[31] Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Kyoung-Ho Moon, and Jae-Whui Kim, "A Calibration-Free 14b 70MS/s 3.3mm2 235mW 0.13um CMOS Pipeline ADC with High-Matching 3-D Symmetric Capacitors," IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, pp. 485-488, Sept. 2006. click

 

[32] Young-Jae Cho, Doo-Hwan Sa, Yong-Woo Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Seung-Hoon Lee, Young-Deuk Jeon, Seung-Chul Lee, and Jong-Kee Kwon, " A 10b 25MS/s 4.8mW 0.13um CMOS ADC for Digital Multimedia Broadcasting Applications," IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, pp. 497-500, Sept. 2006. click

 

[33] Young-Jae Cho, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Ju Kim, Kyoung-Jun Moon, Seung-Hoon Lee, Seok-Bong Hyun, Seong-Su Park, "A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore, pp. 339-342, Dec. 2006.

 

[34] Kyung-Hoon Lee, Young-Jae Cho, Hee-Cheol Choi, Yong-Hyun Park, Doo-Hwan Sa, Young-Lok Kim, Seung-Hoon Lee, "A 14b 100MS/s 3.4mm2 145mW 0.18um CMOS Pipeline A/D Converter," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Singapore, pp.  351-354, Dec. 2006.

 

[35] Young-Ju Kim, Hee-Cheol Choi, Si-Wook Yoo, Seung-Hoon Lee, Dae-Young Chung, Kyoung-Ho Moon, Ho-jin Park, and Jae-Whui Kim, "A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC," IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, pp. 185-188, Sept. 2007. click

 

[36] Young-Ju Kim, Hee-Cheol Choi, Pil-Seon Yoo, and Seung-Hoon Lee, "A 10b 120MS/s 0.18um CMOS Pipeline A/D Converter Based on a Supply-Insensitive CMOS Reference Circuit," Asia and South Pacific Design Automation Conference (ASP-DAC), Student Forum(Travel Grants $300), Seoul, Korea, Jan. 2008. click

 

[37] Hee-Cheol Choi, Young-Ju Kim, Se-Won Lee, Jae-Yeol Han, Young-lok Kim, and Seung-Hoon Lee,"A 52mW 0.56mm2 1.2V 12b 120MS/s SHA-Free Dual-Channel Nyquist ADC Based on Mid-Code Calibration," IEEE International Symposium on Circuits and Systems (ISCAS), Seattle, USA, pp.  9 -12, May 2008. click

 

[38] Hee-Cheol Choi, Young-Ju Kim, Myung-Hwan Lee, Young-Lok Kim, and Seung-Hoon Lee,"A 12b 50MS/s 10.2mA 0.18μm CMOS Nyquist ADC with a Fully Differential Class-AB Switched OP-AMP," IEEE Symposium on  VLSI Circuits, Honolulu, Hawaii USA, pp. 220-221, June 2008. click

 

[39] Young-Ju Kim, Hee-Cheol Choi, Pil-Seon Yoo, Dong-Suk Lee, Joong-Ho Choi, and Seung-Hoon Lee,"A Low Offset Rail-to-Rail 12b 2MS/s 0.18μm CMOS Cyclic ADC," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Macao, China, pp. 17-20, Dec. 2008, invited. click

 

[40] Young-Ju Kim, Hee-Cheol Choi, Kyung-Hoon Lee, Gil-Cho Ahn, Seung-Hoon Lee, Ju-Hwa Kim, Kyoung-Jun Moon, Michael Choi, Kyoung-Ho Moon, Ho-Jin Park, and Byeong-Ha Park, "A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC Based on Multi-Stage Amplifiers," IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, pp. 271-274, Sept. 13-16, 2009. click

 

[41] Beom-Soo Park, Seung-Hak Ji, Min-Ho Choi, Kyung-Hoon Lee, Gil-Cho Ahn, and Seung-Hoon Lee, "A 10b 100MS/s 25.2mW 0.18μm CMOS ADC With Various Circuit Sharing Techniques," International SoC Design Conference (ISOCC), pp. 329-332, Nov. 22-24, 2009. click

 

[42] Young-Ju Kim, Kyung-Hoon Lee, Seung-Hak Ji, Yi-Gi Kwon, Seung-Hoon Lee, Kyoung-Jun Moon, Michael Choi, Ho-Jin Park, and Byeong-Ha Park, "A 10b 120MS/s 45nm CMOS ADC Using A Re-Configurable Three-Stage Switched Op-Amp," IEEE Custom Integrated Circuits Conference (CICC), San Jose, California, pp. 563-566, Sept. 19-22, 2010. click

 

[43] Yi-Gi Kwon, Seung-Hoon Lee, Young-Deuk Jeon, and Jong-Kee Kwon, "A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC With a 2-D INL Bounded Switching Scheme," International SoC Design Conference (ISOCC), pp. 198-200, Nov. 22-23, 2010. click

 

[44] Chang-Seob Shin, Min-Ho Yoon, Kang-Il Cho, Young-Ju Kim, Kwang-Soo Kim, Seung-Hoon Lee, and Gil-Cho Ahn, "A 6.25 MHz BW 8-OSR Fifth-Order Single-Stage Sigma-Delta ADC," IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, pp. 1117-1120, May 15-18, 2011. click

 

[45] Sung-Meen Myung, Yi-Gi Kwon, Sang-Pil Nam, Hyo-Jin Kim, and Seung-Hoon Lee, "A Circuit-Shared Double-Channel Low-Power 10b 170MS/s 0.18um CMOS ADC," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Gyeongjoo, Korea, pp. 279-282, June 19-22, 2011. click

 

[46] Dong-Hyun Hwang, Jung-Eun Song, Sang-Pil Nam, Hyo-Jin Kim, Tai-Ji An, Kwang-Soo Kim, and Seung-Hoon Lee, "A Range-Scaled 13b 100MS/s 0.13um CMOS SHA-Free ADC Based on a Single Reference," International SoC Design Conference (ISOCC), pp. 62-65, Nov. 17-18, 2011. click

 

[47] Sang-Pil Nam, Yong-Min Kim, Dong-Hyun Hwang, Hyo-Jin Kim, Tai-Ji An, Jun-Sang Park, Suk-Hee Cho, Gil-Cho Ahn, and Seung-Hoon Lee, "A 10b 1MS/s-to-10MS/s 0.11um CMOS SAR ADC for Analog TV Applications," International SoC Design Conference (ISOCC), pp. 124-127, Nov. 4-7, 2012. click

 

[48] Tai-Ji An, Jun-Sang Park, Yong-Min Kim, Suk-Hee Cho, Gil-Cho Ahn, and Seung-Hoon Lee, "10b 150MS/s 0.4mm2 45nm CMOS ADC Based on Process-Insensitive Amplifiers," IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, pp. 361-364, May 19-23, 2013. click

 

[49] Suk-Hee Cho, Tai-Ji An, Yong-Min Kim, Ji-Hyun Roh, Mun-Kyo Lee, Sun-Phil Nah, and Seung-Hoon Lee, "12b 100MS/s 1.1V 0.43mm2 ADC optimized in a 45nm CMOS technology," International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC), Yeosu, Korea, pp. 180-183, June 30-July 3, 2013. click

 

[50] Jun-Sang Park, Tai-Ji An, Yong-Min Kim, Suk-Hee Cho, Hyun-Sun Shim, Woo-Jin Jang, Yong-Jin Shin, Jun-Hyup Lee, Gil-Cho Ahn, and Seung-Hoon Lee, "A 10b 50MS/s 90nm CMOS Skinny-Shape ADC Using Variable References for CIS Applications," International SoC Design Conference (ISOCC), pp. 80-82, Nov. 17-19, 2013. click

 

[51] Jong-Min Jeong, Tai-Ji An, Hee-Wook Shin, Gi-Wook Lee and Seung-Hoon Lee, "A 0.16mm2 12b 30MS/s 0.18um CMOS SAR ADC Based on Low-Power Composite Switching," International SoC Design Conference (ISOCC), pp. 77-78, Nov. 2-5, 2015. click.

 

[52] Jae-Hyeok Byun, Jun-Sang Park, Won-Kang Kim, Young-Sae Cho, Young-Sub Lee, and Seung-Hoon Lee, "A 12b 60MS/s 0.11um Flash-SAR ADC Using a Mismatch-Free Shared Sampling Network," International SoC Design Conference (ISOCC), pp. 79-80, Nov. 2-5, 2015.click. 

  

 

 

 

 

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