International Journal Paper / International Conference Paper

Domestic Journal Paper / Domestic Conference Paper

Workshop & Seminar & Award / Technical Report

Books & Patents & IP Registration

 

International Journal Paper

bar06_solid1x1_red.gif

 

[1] S.H. Lee and B.S. Song, "A Direct Code Error Calibration Technique for Two-Step Flash A/D Converters," IEEE Trans. Circuits Syst., vol. 36, no. 6, pp. 919-922, June 1989.

 

[2] B.S. Song, S.H. Lee, and M.F. Tompsett, "A 10-b 15-MHz CMOS Recycling Two-Step A/D converter," IEEE J. Solid State Circuits, vol. 25, no. 6, pp. 1328-1338, Dec. 1990.

 

[3] S.H. Lee and B.S. Song, "Digital-Domain Calibration of Multistep Analog-to-Digital Converters," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1679-1688, Dec. 1992.

 

[4] S.H. Lee and B.S. Song, "Interstage Gain Proration Technique for Digital-Domain Multi-Step ADC Calibration," IEEE Trans. Circuits Syst. II, vol. 41, no. 1, pp. 12-18, Jan. 1994.

 

[5] G.C. Ahn, H.C. Choi, S.H. Lee, and C.D. Lee, "A 12-b, 10-MHz, 250-mW CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 2030- 2035, Dec. 1996.

 

[6] D.Y. Chang and S.H. Lee, "Design Techniques for a Low-Power Low-Cost CMOS A/D Converter," IEEE J. Solid-State Circuits, vol. 33, no.8, pp. 1244-1248, Aug. 1998.

 

[7] J.R. Park and S.H. Lee, "A 3V 10b 20MHz A/D Converter Based On a New CMOS On-Chip Current Reference," Journal of Electrical Engineering and Information Science, vol. 3, no. 5, pp. 573-579, Oct. 1998.

 

[8] B. L. Jeon and S. H. Lee, "A 10b 50MHz 320mW CMOS A/D CONVERTER FOR VIDEO APPLICATIONS," IEEE Trans. Consumer Electronics, vol. 45, no, 1, pp. 252-258, Feb. 1999.

 

[9] S.H. Lee and Y. Jee, "A Temperature and Supply-Voltage Insensitive CMOS Current Reference," IEICE Trans. Electronics, vol. E82-C, no. 8, pp.1562-1566, Aug. 1999.

 

[10] Y. J. Cha, J. K. Lee, and S. H. Lee, "Digitally-controlled automatic gain control circuits for CMOS CCD camera interface," IET Electronics Letters, vol. 35, no, 22, pp. 1909-1910, Oct. 1999.

 

[11] Y. D. Jeon and S. H. Lee, "Acquisition time minimization techniques for high-speed analog signal processing," IET Electronics Letters, vol. 35, no. 23, pp. 1990-1991, Nov. 1999.

 

[12] J. Park, S. C. Lee, and Seung-Hoon Lee, "3V 10b 70MHz CMOS D/A converter for video applications," IET Electronics Letters, vol. 35, no. 24, pp. 2071-2073, Nov. 1999.

 

[13] T. H. Oh and S. H. Lee, "Single-Chip CMOS CCD Camera Interface Based on Digitally Controlled Capacitor-Segment Combination," IEEE Trans. Circuits Syst. II, vol. 47, no. 11, pp. 1338-1343, Nov. 2000.

 

[14] S. C. Lee, J. Park, J. S. Yoon, and S. H. Lee, "A 3 V 10b 100 MS/s DIGITAL-TO-ANALOG CONVERTER FOR CABLE MODEM APPLICATIONS," IEEE Trans. Consumer Electronics, vol. 46, no, 4, pp. 1043-1047, Nov. 2000.

 

[15] S. H. Lee, J. W. Moon, and S.H. Lee, "An 8b 52 MHz Double-Channel CMOS Subranging A/D Converter for DSL Applications," IEICE Trans. Electronics, vol. E84-C, no. 4, pp. 470-474, April 2001.

 

[16] S. H. Lee and J. S. Lee, "Comments on "Comments on 'Interstage Gain-Proration Technique for Digital-Domain Multistep ADC Calibration'"," IEEE Trans. Circuits Syst. II, vol. 48, no. 7, pp. 745-749, July 2001

 

[17] J. S. Lee, S. H. Joo, and S. H. Lee, "Resolution Enhancement Techniques for High-Speed Multi-Stage Pipelined ADC's Based on a Multi-Bit Multiplying DAC," IEICE Trans. Electronics, vol. E84-C, no. 8, pp. 1092-1099, Aug. 2001.

 

[18] S. C. Lee and S. H. Lee, "A LOW-RIPPLE SWITCHED-CAPACITOR DC-DC UP CONVERTER FOR LOW-VOLTAGE APPLICATIONS," IEICE Trans. Electronics, vol. E84-C, no. 8, pp. 1100-1103, Aug. 2001.

 

[19] Jeong-Woong Moon and Seung-Hoon Lee, "An 8b 200MHz Time-Interleaved Subranging ADC Based on a Single-Poly Digital CMOS Process," IEICE Trans. Electronics, vol. E86-C, no. 3, pp. 506-513, Mar. 2003.

 

[20] Hyuen-Hee Bae, Jin-Sik Yoon, and Seung-Hoon Lee, "A 3V 12b 100MS/s CMOS D/A Converter for High-Speed Communication Systems," Journal of Semiconductor Technology and Science, vol. 3, no. 4, pp. 211-216, Dec. 2003.

 

[21] Sang-Min Yoo, Jong-Bum Park, Seung-Hoon Lee, and Un-Ku Moon, "A 2.5-V 10-b 120-MSample/s CMOS Pipelined ADC Based on Merged-Capacitor Switching," IEEE Trans. Circuits Syst. II, vol. 51, no. 5, pp. 269-275, May 2004.

 

[22] Jong-Bum Park, Sang-Min Yoo, Se-Won Kim, Young-Jae Cho, and Seung-Hoon Lee, "A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D Converter With 400-MHz Input Bandwidth," IEEE J. Solid-State Circuits, vol. 39, no. 8,  pp. 1335-1337, Aug. 2004.

 

[23] Young-Jae Cho, Hyuen-Hee Bae, and Seung-Hoon Lee, "An 8b 220 MS/s 0.25 μm CMOS Pipeline ADC with On-Chip RC-Filter Based Voltage References ," IEICE Trans. Electronics, vol. E88-C, no. 4, pp. 768-772, April 2005.

 

[24] Young-Jae Cho and Seung-Hoon Lee, "An 11b 70-MHz 1.2-mm2 49-mW 0.18-μm CMOS ADC With On-Chip Current/Voltage References," IEEE Trans. Circuits Syst. I, vol. 52, no. 10, pp.1989-1995, Oct. 2005. 

 

[25] Byoung-Han Min, Young-Jae Cho, Hee-Sung Chae, Hee-Won Park, and Seung-Hoon Lee, "A 10b 100 MS/s 1.4mm2 56 mW 0.18 μm CMOS A/D Converter with 3-D Fully Symmetrical Capacitors," IEICE Trans. Electronics, vol. E89-C, no. 5, pp. 630-635, May 2006.

 

[26] Young-Jae Cho, Se-Won Kim, Kyung-Hoon Lee, Hee-Cheol Choi, Young-Lok Kim, and Seung-Hoon Lee, "An Embedded 8b 240 MS/s 1.36 mm2 104 mW 0.18 μm CMOS ADC for DVDs with Dual-Mode Inputs," IEICE Trans. Electronics, vol. E89-C, no. 5, pp. 636-641, May 2006.

 

[27] Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jong-Dae Kim, and Seung-Hoon Lee, "A 10-bit 400-MS/s 160-mW 0.13-μm CMOS Dual-Channel Pipeline ADC Without Channel Mismatch Calibration," IEEE J. Solid-State Circuits, vol. 41, no. 7, pp. 1596-1605, July 2006.

 

[28] Kyung-Hoon Lee, Hee-Cheol Choi, Kyoung-Jun Moon, Young-Lok Kim and Seung-Hoon Lee, "Calibration-free 14b 70MS/s 0.13 μm CMOS pipeline A/D converters based on high-matching 3D symmetric capacitors," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 43, no. 6, pp. 340-341, Mar. 2007. click

 

[29] Young-Ju Kim, Young-Jae Cho, Doo-Hwan Sa, and Seung-Hoon Lee, "A 10b 200MS/s 1.8mm2 83mW 0.13μm CMOS ADC Based on Highly Linear Integrated Capacitors," IEICE Trans. Electronics, vol. E90-C, no. 10, pp. 2037-2043, Oct. 2007. click

 

[30] Young-Ju Kim, Hee-Cheol Choi, Seung-Hoon Lee, and Dongil "Dan" Cho, "A 12b 200kS/s 0.52mA 0.47mm2 Algorithmic A/D Converter for MEMS Applications,"  IEICE Trans. Electronics, vol. E91-C, no. 2, pp. 206-212, Feb. 2008. click

 

[31] Hee-Cheol Choi, Young-Ju Kim, Si-Wook Yoo, Sun-Young Hwang, and Seung-Hoon Lee, "A Programmable 0.8-V 10-bit 60-MS/s 19.2-mW 0.13-μm CMOS ADC Operating Down to 0.5V," IEEE Trans. Circuits Syst. II, vol. 55, no. 4, pp. 319-323, April 2008. click

 

[32] Hee-Cheol Choi, Young-Ju Kim, Woo-Joo Kim, Younglok Kim, and Seung-Hoon Lee, "A 10 b 120 MS/s 108 mW 0.18 μm CMOS ADC with a PVT-insensitive current reference," Analog Integrated Circuits and Signal Processing, vol 58, no. 2, pp. 115-121, Feb. 2009. click

 

[33] Hee-Cheol Choi, Young-Ju Kim, Gil-Cho Ahn, and Seung-Hoon Lee, "A 1.2-V 12-b 120-MS/s SHA-Free Dual-Channel Nyquist ADC Based on Midcode Calibration," IEEE Trans. Circuits Syst. I, vol. 56, no. 5, pp. 894-901, May. 2009. click

 

[34] Young-Ju Kim, Kyung-Hoon Lee, Myung-Hawn Lee, and Seung-Hoon Lee, "A 0.31 pJ/Conversion-Step 12-Bit 100MS/s 0.13μm CMOS A/D Converter for 3G Communication Systems,"  IEICE Trans. Electronics, vol. E92-C, no. 9, pp. 1194-1200, Sept. 2009. click

 

[35] Hee-Cheol Choi, Gil-Cho Ahn, Joong-Ho Choi, and Seung-Hoon Lee, "A Rail-to-Rail Input 12b 2 MS/s 0.18 μm CMOS Cyclic ADC for Touch Screen Applications," Journal of Semiconductor Technology and Science, vol. 9, no. 3, pp. 160-165, Sept. 2009. click

 

[36] Kyung-Hoon Lee, Young-Ju Kim, Kwang-Soo Kim, and Seung-Hoon Lee, "14 bit 50 MS/s 0.18 μm CMOS pipeline ADC based on digital error calibration," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 45,  no. 21, pp. 1067-1069, Oct. 2009. click

 

[37] Hee-Cheol Choi, Young-Ju Kim, Kyung-Hoon Lee, Younglok Kim, and Seung-Hoon Lee, "A 10b 25MS/s 4.8mW 0.13μm CMOS ADC with switched-bias power-reduction techniques," International Journal of Circuit Theory and Applications, vol. 37, no. 9, pp. 955-967, Nov. 2009. click

 

[38] Kyung-Hoon Lee, Se-Won Lee, Young-Ju Kim, Kwang-Soo Kim, and Seung-Hoon Lee, "Ten-bit 100 MS/s 24.2 mW 0.8 mm2 0.18 μm CMOS pipeline ADC based on maximal circuit sharing schemes," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 45, no. 25, pp. 1296-1297, Dec. 2009. click

 

[39] Young-Ju Kim and Seung-Hoon Lee, "A 12 b 8 kS/s 16 μW 0.35 μm CMOS algorithmic ADC for sensor interface in ubiquitous environments,"Analog Integrated Circuits and Signal Processing, vol. 62, no. 2, pp. 205-213, Feb. 2010. click

 

 [40] Young-Ju Kim, Hee-Cheol Choi, Gil-Cho Ahn, and Seung-Hoon Lee, "A 12 bit 50 MS/s CMOS Nyquist A/D Converter With a Fully Differential Class-AB Switched Op-Amp," IEEE J. Solid-State Circuits, vol. 45, no. 3, pp. 620-628, Mar. 2010. click

 

[41] Hariprasath Venkatram, Jon Guerber, Seung-Hoon Lee, and Un-Ku Moon, "Merged capacitor switching based SAR ADC with highest switching energy-efficiency," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 46, no. 9, pp. 620-621, April 2010. click

 

[42] Min-Ho Choi, Gil-Cho Ahn, and Seung-Hoon Lee, "12b 50 MS/s 0.18 μm CMOS ADC with highly linear input variable gain amplifier," IET (The Institution of Engineering and Technology) Electronics Letters, vol. 46, no. 18, pp. 1254-1256, Sept. 2010. click

 

[43] Hee-Cheol Choi, Pil-Seon Yoo, Gil-Cho Ahn, and Seung-Hoon Lee, "A 14b 150MS/s 140mW 2.0mm2 0.13μm CMOS A/D Converter for software-defined radio systems," International Journal of Circuit Theory and Applications, vol. 39, issue 2, pp. 135-147, Feb. 2011. click

 

[44] Hye-Lim Park, Yi-Gi Kwon, Min-Ho Choi, Younglok Kim, Seung-Hoon Lee, Young-Deuk Jeon, and Jong-Kee Kwon, "A 6b 1.2 GS/s 47.8 mW 0.17 mm2 65 nm CMOS ADC for High-Rate WPAN Systems," Journal of Semiconductor Technology and Science, vol. 11, no. 2, pp. 95-103, June 2011. click

 

[45] Byeong-Woo Koo, Seung-Jae Park, Gil-Cho Ahn, and Seung-Hoon Lee, "A Single Amplifier-Based 12-bit 100MS/s 1V 19mW 0.13μm CMOS ADC with Various Power and Area Minimized Circuit Techniques," IEICE Trans. Electronics, vol. E94-C, no. 8, pp. 1282-1288, Aug. 2011. click

 

[46] Kyung-Hoon Lee, Kwang-Soo Kim, and Seung-Hoon Lee, "A 12b 50 MS/s 21.6 mW 0.18 μm CMOS ADC Maximally Sharing Capacitors and Op-Amps," IEEE Trans. Circuits Syst. I, vol. 58, no. 9, pp. 2127-2136, Sept. 2011. click

 

[47] Young-Ju Kim and Seung-Hoon Lee, "A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier," Analog Integrated Circuits and Signal Processing, vol. 72, no. 1, pp. 75-87, July 2012. click

 

[48] Hye-Lim Park, Sung-Meen Myung, Younglok Kim, and Seung-Hoon Lee, "An 8b 250MS/s 0.13μm CMOS ADC using variable references for VGA-to-WUXGA scaler chips," Analog Integrated Circuits and Signal Processing, vol. 73, no. 1, pp. 233-242, Oct. 2012. click

 

[49] Dong-Hyun Hwang, Jung-Eun Song, Sang-Pil Nam, Hyo-Jin Kim, Tai-Ji An, Kwang-Soo Kim, and Seung-Hoon Lee, "A Range-Scaled 13b 100 MS/s 0.13 um CMOS SHA-Free ADC Based on a Single Reference," Journal of Semiconductor Technology and Science, vol. 13, no. 2, pp. 98-107, Apr. 2013. click 

 

[50] Hye-Lim Park, Min-Ho Choi, Sang-Pil Nam, Tai-Ji An, and Seung-Hoon Lee, "A mismatch-error minimized four-channel time-interleaved 11 b 150 MS/s pipelined SAR ADC," Analog Integrated Circuits and Signal Processing, vol. 76, no. 1, pp. 1-13, July 2013. click

 

[51] Hyo-Jin Kim, Tai-Ji An, Sung-Meen Myung, and Seung-Hoon Lee, "Time-Interleaved and Circuit-Shared Dual-Channel 10 b 200 MS/s 0.18 μm CMOS Analog-to-Digital Convertor," IEEE Trans. VLSI systems, vol. 21, no. 12, pp. 2206-2213, Dec. 2013. click

 

[52] Jun-Sang Park, Tai-Ji An, Suk-Hee Cho, Yong-Min Kim, Gil-Cho Ahn, Ji-Hyun Roh, Mun-Kyo Lee, Sun-Phil Nah, and Seung-Hoon Lee, "A 12b 100MS/s Three-Step Hybrid Pipeline ADC Based on Time-Interleaved SAR ADCs," Journal of Semiconductor Technology and Science, vol. 14, no. 2, pp. 189-197, Apr. 2014. click

 

[53] Yong-Min Kim, Jun-Sang Park, Yong-Jin Shin, and Seung-Hoon Lee, "An 87 fJ/conversion-step 12 b 10 MS/s SAR ADC using a minimum number of unit capacitors," Analog Integrated Circuits and Signal Processing, vol. 80, no. 1, pp. 49-57, July 2014. click

 

[54] Suk-Hee Cho, Jun-Sang Park, Gil-Cho Ahn, and Seung-Hoon Lee, "A 14-10 b dual-mode low-noise pipeline ADC for high-end CMOS image sensors," Analog Integrated Circuits and Signal Processing, vol. 80, no. 3, pp. 437-447, Sept. 2014.  click

 

[55] Jun-Sang Park, Jong-Min Jeong, Tai-Ji An, Gil-Cho Ahn, and Seung-Hoon Lee, "Range-Scaled 14b 30MS/s Pipeline-SAR Composite ADC for High-Performance CMOS Image Sensors," Journal of Semiconductor Technology and Science, vol. 16, no. 1, pp. 70-79, Feb. 2016. click

 

[56] Tai-Ji An, Gil-Cho Ahn, and Seung-Hoon Lee, "High-efficiency low-noise pulse-width modulation DC-DC buck converter based on multi-partition switching for mobile system-on-a-chip applications," IET (The Institution of Engineering and Technology) Power Electronics, vol. 9, no. 3, pp. 559-567, Mar. 2016. click

 

[57] Tai-Ji An, Young-Sea Cho, Jun-Sang Park, Gil-Cho Ahn, and Seung-Hoon Lee, "A Two-channel 10b 160 MS/s 28 nm CMOS Asynchronous Pipelined-SAR ADC with Low Channel Mismatch," Journal of Semiconductor Technology and Science, vol. 17, no. 5, pp. 636-647, Oct. 2017. click

 

 

 

 

 서울특별시 마포구 백범로 35(신수동) 서강대학교 R관 905호 Tel. 02-715-6129       Webmaster

※본 홈페이지 내의 연구개발정보, 전자우편주소 등 개인정보 등을 무단 수집시 관련법의 제제를 받을 수 있습니다.